In recent years, with an improvement in the throughput of computers, there arises a problem of an increase in the power consumption of processors installed in the computers. One of techniques for reducing the power consumption of processors is Dynamic Voltage and Frequency Scaling (DVFS). A processor using the DVFS technique operates at a plurality of performance levels with different clock frequencies and/or different voltages. The performance level may be called P-state. As a clock frequency or voltage is lowered (i.e., a performance level is decreased), the power consumption of a processor will be reduced. Therefore, dynamically decreasing a performance level results in reducing wasteful power consumption of a processor. However, when a processor operates at a low performance level, the processing speed thereof slows down accordingly.
Some types of system software such as Basic Input/Output System (BIOS), Operating System (OS), etc. are capable of switching the performance level of a processor according to processor utilization. For example, when the processor utilization goes down, such system software decreases the performance level of the processor, thereby reducing power consumption. When the processor utilization goes up, on the other hand, the system software increases the performance level and waits for the processor utilization to go down.
In many cases, it is determined at predetermined regular intervals whether to switch the performance level of a processor. For example, the system software confirms processor utilization at the predetermined regular intervals, and determines according to the confirmed processor utilization whether to switch the performance level. In connection with this, there is proposed a semiconductor apparatus that changes the frequency of determining whether to switch a performance level so as not to switch the performance level too frequently. This semiconductor apparatus counts how many times a clock frequency and voltage were changed in the past, and decreases the frequency of making the determination if the count is high and, on the other hand, increases the frequency of making the determination if the count is low.
Further, there is also proposed a power management method in which an OS monitors processor information and selects the run state of a processor from among a plurality of run states having different performance levels, according to the processor information. In this power management method, the OS predicts future processor information based on sampled past processor information, and selects the run state of the processor based on an average of the past and future processor information. Still further, there is proposed a system for selecting a target P-state based on a percentage of time a processor is busy. This system periodically reduces the selection of the target P-state while the processor is 100% busy.
Please refer to Japanese Laid-open Patent Publication No. 2004-29983, International Publication Pamphlet No. WO 2004/102363, and Japanese Laid-open Patent Publication No. 2009-110509.
By the way, load (for example, the amount of requests received per unit time from other computers) on a computer is often inconstant and may vary with periodicity. In this case, a mismatch between the load and the performance level of a processor may occur and continue depending on a period of load variation, and therefore efficiency of processor utilization is reduced.
For example, assume that load on a computer rapidly rises when a processor operates at a low performance level. In this case, the performance level remains low until it is determined next time whether to switch the performance level. As a result, the number of pending requests increases, which causes long response delays. After determining whether to switch the performance level, the performance level of the processor is increased and the number of pending requests decreases. Then, even if the load on the computer rapidly falls, the performance level remains high until it is determined next time whether to switch the performance level. As a result, the processor consumes power wastefully in view of the load.
Such a mismatch between the load and the performance level of a processor continues if the period of load variation is equal to or approximate to an interval for determining whether to switch the performance level. More specifically, a state where the load rises but the performance level of the processor remains low and a state where the load falls but the performance level of the processor remains high appear alternately and repeatedly. That is to say, the DVFS, which is a technique for power saving of a processor, may cause a problem of a reduction in the efficiency of processor utilization. On the other hand, if a fixed short interval is used for determining whether to switch the performance level, an overhead for controlling the performance level increases and the power saving effect of the DVFS is reduced.